As the feature size of MOSFET processes shrink, the MOSFET sub-threshold drain-to-source leakage current when the transistor is supposedly turned off becomes increasingly large. In analog circuits where it is critical for a node to stay at high impedance, this increased leakage current may no longer be ignored. When the devices connected to the high impedance node draw large enough leakage currents, the performance of the circuit may suffer significantly. For instance, in a phase-locked loop (PLL), the devices connected to the high-impedance node of the loop filter may draw enough current when the devices are supposedly off to cause jitter in the PLL output.
Therefore, there is a need in the art for improved analog circuits that are fabricated using small feature-sized MOSFET processes. In particular, there is a need for circuits that reduce the sub-threshold leakage currents in small MOSFET devices connected to sensitive analog circuit nodes.